Research Professor School of Microelectronics University of Science and Technology of China Office: Room 214, Ronghe Building, North Campus Email: xuqi[@]ustc.edu.cn

Biography

I'm currently a research professor in the School of Microelectronics, University of Science and Technology of China (USTC). I received my PH.D. in Electronic Science and Technology from USTC in 2018.

My research interests include AI for EDA, especially for physical design, and reliability design for 3D-IC.[My Resume] [Google Scholar]

Publications

Journal papers

• [J31] Peng Xu, Rong Sun, Song Chen, Qi Xu*, Bei Yu, “DaVinci: Performance-Driven Analog Routing via Multi-modality Guidance Prediction”, accepted by IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2026.

• [J30] Weiran Chen, Qi Xu*, Song Chen, Yi Kang, Bei Yu, “Scalable High-Fidelity Solver for Large-Scale ReRAM Crossbar Arrays Under I–V Nonlinearity”, accepted by ACM Transactions on Design Automation of Electronic Systems (TODAES), 2026.

• [J29] Rong Sun, Qi Xu*, Song Chen, Yi Kang, Bei Yu, “GoSteiner: Constructing Rectilinear Steiner Minimum Tree on Directed Graph”, ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 31, no. 3, pp. 58:1-58:20, 2026.

• [J28] Donger Luo, Qi Sun, Peng Xu, Su Zheng, Qi Xu, Tinghuan Chen, Bei Yu, Hao Geng, “Attention-Based EDA Tool Parameter Explorer: From Hybrid Parameters to Multi-QoR Metrics”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 45, no. 2, pp. 691-704, 2026.

• [J27] Biao Liu, Chen Jiang, Qi Xu, Hailong Yao, Tsung-Yi Ho, Bo Yuan, “Efficient Routing-based Synthesis for Digital Microfluidic Biochips via Reinforcement Learning”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 45, no. 1, pp. 162-175, 2026.

• [J26] Weiran Chen, Zaitian Chen, Bei Yu, Song Chen, Yi Kang, Qi Xu*, “Real-Time Compensation Framework for Large-Scale ReRAM-Based Sparse LU Factorization”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 45, no. 1, pp. 309-322, 2026.

• [J25] Qi Xu, Lijie Wang, Jing Wang, Lin Cheng, Song Chen, Yi Kang, “Graph Attention-Based Symmetry Constraint Extraction for Analog Circuits”, IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), vol. 71, no. 8, pp. 3754-3763, 2024.

• [J24] Bo Yang, Qi Xu*, Hao Geng, Song Chen, Bei Yu, Yi Kang, “Floorplanning with Edge-Aware Graph Attention Network and Hindsight Experience Replay”, ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 29, no. 3, pp. 56:1-56:17, 2024.

• [J23] Junpeng Wang, Mengke Ge, Bo Ding, Qi Xu, Song Chen, Yi Kang, “NicePIM: Design Space Exploration for Processing-In-Memory DNN Accelerators with 3D-Stacked-DRAM”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 43, no. 5, pp. 1456-1469, 2024.

• [J22] Bo Ding, Jinglei Huang, Junpeng Wang, Qi Xu, Song Chen, Yi Kang, “Task modules Partitioning, Scheduling and Floorplanning for Partially Dynamically Reconfigurable Systems with Heterogeneous Resources”, ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 28, no. 6, pp. 103:1-103:26, 2023.

• [J21] Yongtian Bi, Qi Xu*, Hao Geng, Song Chen, Yi Kang, “AD²VNCS: Adversarial Defense and Device Variation-Tolerance in Memristive Crossbar-Based Neuromorphic Computing Systems”, ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 29, no. 1, pp. 8:1-8:19, 2023.

• [J20] Xiaobing Ni, Mengke Ge, Yongjin Tao, Wendi Sun, Feixiang Duan, Xuefei Bai, Qi Xu, Song Chen, Yi Kang, “BusMap: Application Mapping with Bus Routing for Coarse-Grained Reconfigurable Array”, IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), vol. 70, no. 8, pp. 3054-3058, 2023.

• [J19] Yongtian Bi, Qi Xu*, Hao Geng, Song Chen, Yi Kang, “Resist: Robust Network Training for Memristive Crossbar-Based Neuromorphic Computing Systems”, IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), vol. 70, no. 6, pp. 2221-2225, 2023.

• [J18] Chen Jiang, Rongquan Yang, Qi Xu, Hailong Yao, Tsung-Yi Ho, Bo Yuan, “A Cooperative Multi-agent Reinforcement Learning Framework for Droplet Routing in Digital Microfluidic Biochips”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 42, no. 9, pp. 3007-3020, 2023.

• [J17] Junpeng Wang, Haitao Du, Bo Ding, Qi Xu, Song Chen, Yi Kang, “DDAM: Data Distribution-Aware Mapping of CNNs on Processing-In-Memory Systems”, ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 28, no. 3, pp. 36:1-36:30, 2023.

• [J16] Bo Ding, Jinglei Huang, Qi Xu, Junpeng Wang, Song Chen, Yi Kang, “Memory-aware Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable Systems”, ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 28, no. 1, pp. 7:1-7:21, 2023.

• [J15] Qi Xu, Junpeng Wang, Bo Yuan, Qi Sun, Song Chen, Bei Yu, Yi Kang, Feng Wu, “Reliability-Driven Memristive Crossbar Design in Neuromorphic Computing Systems”, IEEE Transactions on Automation Science and Engineering (TASE), vol. 20, no. 1, pp. 74-87, 2023.

• [J14] Qi Xu, Hao Geng, Tianming Ni, Song Chen, Bei Yu, Yi Kang, Xiaoqing Wen, “Fortune: A New Fault-Tolerance TSV Configuration in Router-based Redundancy Structure”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 41, no. 10, pp. 3182-3187, 2022.

• [J13] Qi Xu, Hao Geng, Song Chen, Bo Yuan, Cheng Zhuo, Yi Kang, Xiaoqing Wen, “GoodFloorplan: Graph Convolutional Network and Reinforcement Learning Based Floorplanning”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 41, no. 10, pp. 3492-3502, 2022.

• [J12] Qi Xu, Wenhao Sun, Song Chen, Yi Kang, Xiaoqing Wen, “Cellular Structure-Based Fault-Tolerance TSV Configuration in 3D-IC”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 41, no. 5, pp. 1196-1208, 2022.

• [J11] Hao Geng, Yuzhe Ma, Qi Xu, Jin Miao, Subhendu Roy, Bei Yu, “High-Speed Adder Design Space Exploration via Graph Neural Processes”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 41, no. 8, pp. 2657-2670, 2022.

• [J10] Mengke Ge, Xiaobing Ni, Qi Xu, Jinglei Huang, Song Chen, Yi Kang, Feng Wu, “Synthesizing Brain-Network-Inspired Interconnections for Large-Scale Network-on-Chips”, ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 27, no. 1, pp. 9:1-9:30, 2021.

• [J9] Qi Xu, Song Chen, Hao Geng, Bo Yuan, Bei Yu, Feng Wu, Zhengfeng Huang, “Fault Tolerance in Memristive Crossbar-Based Neuromorphic Computing Systems”, Integration, the VLSI Journal, vol. 70, pp. 70-79, 2020.

• [J8] Tianming Ni, Hao Chang, Tai Song, Qi Xu*, Zhengfeng Huang, Huaguo Liang, et.al, “Non-intrusive Online Distributed Pulse Shrinking Based Interconnect Testing in 2.5D IC”, IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), vol. 67, no. 11, pp. 2657-2661, 2020.

• [J7] Song Chen*, Mengke Ge, Zhigang Li, Jinglei Huang, Qi Xu*, Feng Wu, “Generalized Fault-Tolerance Topology Generation for Application Specific Network-on-Chips”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 39, no. 6, pp. 1191-1204, 2020.

• [J6] Song Chen , Jinglei Huang, Xiaodong Xu, Bo Ding, Qi Xu, “Integrated Optimization of Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable Systems”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 39, no. 1, pp. 199-212, 2020.

• [J5] Qi Xu, Hao Geng, Song Chen, Bei Yu, Feng Wu, “Memristive Crossbar Mapping for Neuromorphic Computing Systems on 3D IC”, ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 25, no. 1, pp. 8:1-8:19, 2019.

• [J4] Song Chen*, Qi Xu*, Bei Yu, “Adaptive 3D-IC TSV Fault Tolerance Structure Generation”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 38, no. 5, pp. 949-960, 2019.

• [J3] Qi Xu, Song Chen, Xiaodong Xu, Bei Yu, “Clustered Fault Tolerance TSV Planning for 3D Integrated Circuits”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 36, no. 8, pp. 1287-1300, 2017.

• [J2] Qi Xu, Song Chen, “Fast Thermal Analysis for Fixed-outline 3D Floorplanning”, Integration, the VLSI Journal, vol. 59, pp. 157-167, 2017.

• [J1] Qi Xu, Song Chen, Bin Li, “Combining the Ant System Algorithm and Simulated Annealing for 3D/2D Fixed-Outline Floorplanning”, Applied Soft Computing, vol. 40, pp. 150-160, 2016.

Conference papers

• [C17] Kai Ma, Zhen Wang, Hongquan He, Qi Xu, Tinghuan Chen, Hao Geng, “LMM-IR: Large-Scale Netlist- Aware Multimodal Framework for Static IR-Drop Prediction”, ACM/IEEE Design Automation Conference (DAC), San Francisco, Jun. 22–25, 2025.

• [C16] Weiran Chen, Qi Xu*, “Robust and Efficient Adversarial Defense in SNNs via Image Purification and Joint Detection”, IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), Hyderabad, India, Apr. 06-11, 2025.

• [C15] Lijie Wang, Jing Wang, Song Chen, Qi Xu*, “AIPlace: Analog IC Placement with Multi-Task Learning Framework”, IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Tokyo, Japan, Jan. 20-23, 2025.

• [C14] Xinfei Liu, Siting Liu, Bei Yu, Song Chen, Qi Xu*, “ThePlace: Thermal-Aware Placement With Operator Learning-Based Ultra-Fast Simulator”, IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Tokyo, Japan, Jan. 20-23, 2025.

• [C13] Lin Chen, Qi Xu, Hu Ding, “OTPlace-Vias: A Novel Optimal Transport Based Method for High Density Vias Placement in 3D Circuits”, ACM/IEEE Design Automation Conference (DAC), San Francisco, Jun. 23-27, 2024.

• [C12] Bing Li, Wendi Sun, Xiaobing Ni, Kaixuan He, Qi Xu*, Song Chen*, Yi Kang, “Parallel Multi-objective Bayesian Optimization Framework for CGRA Microarchitecture”, IEEE/ACM Proceedings Design, Automation and Test in Europe (DATE), Valencia, Spain, Mar. 25-27, 2024.

• [C11] Bo Yang, Qi Xu*, Hao Geng, Song Chen, Yi Kang, “Miracle: Multi-Action Reinforcement Learning-Based Chip Floorplanning Reasoner”, IEEE/ACM Proceedings Design, Automation and Test in Europe (DATE), Valencia, Spain, Mar. 25-27, 2024.

• [C10] Donger Luo, Qi Sun, Qi Xu, Tinghuan Chen, Hao Geng, “Attention-Based EDA Tool Parameter Explorer: From Hybrid Parameters to Multi-QoR metrics”, IEEE/ACM Proceedings Design, Automation and Test in Europe (DATE), Valencia, Spain, Mar. 25-27, 2024.

• [C9] Yang Xiao, Qi Xu, Bo Yuan, “Tolerating Device-to-Device Variation for Memristive Crossbar-Based Neuromorphic Computing Systems: A New Bayesian Perspective”, International Joint Conference on Neural Networks (IJCNN), Queensland, Australia, Jun. 18-23, 2023.

• [C8] Hao Geng, Qi Sun, Qi Xu, Tsung-Yi Ho, Bei Yu, “Mixed-type Wafer Failure Pattern Recognition”, IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), Tokyo Odaiba Miraikan, Jan. 16-19, 2023.

• [C7] Hao Geng, Qi Xu, Tsung-Yi Ho, Bei Yu, “PPATuner: Pareto-driven Tool Parameter Auto-tuning in Physical Design via Gaussian Process Transfer Learning”, ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, Jul. 10-14, 2022.

• [C6] Qi Xu, Junpeng Wang, Hao Geng, Song Chen and Xiaoqing Wen, “Reliability-Driven Neuromorphic Computing Systems Design”, IEEE/ACM Proceedings Design, Automation and Test in Europe (DATE), Virtual Event, France, Feb., 2021.

• [C5] Junpeng Wang, Qi Xu*, Bo Yuan, Song Chen, Bei Yu, Feng Wu, “Reliability-Driven Neural Network Training for Memristive Crossbar-Based Neuromorphic Computing Systems”, IEEE International Symposium on Circuits and Systems (ISCAS), Virtual Event, Spain, Oct., 2020.

• [C4] Mengke Ge, Qi Xu, Huajie Ruan, Xiaobing Ni, Song Chen, Yi Kang, “Synthesizing A Generalized Brain-inspired Interconnection Network for Large-scale Network-on-chip Systems”, ACM Great Lakes Symposium on VLSI (GLSVLSI), Virtual Event, China, Sep., 2020.

• [C3] Qi Xu, Song Chen, Bei Yu, Feng Wu, “Memristive Crossbar Mapping for Neuromorphic Computing Systems on 3D IC”, ACM Great Lakes Symposium on VLSI (GLSVLSI), Chicago, USA, May, 2018.

• [C2] Xiaodong Xu, Qi Xu, Jinglei Huang, Song Chen, “An Integrated Optimization Framework for Partitioning, Scheduling and Floorplanning on Partially Dynamically Reconfigurable FPGAs”, ACM Great Lakes Symposium on VLSI (GLSVLSI), Alberta, Canada, May, 2017.

• [C1] Qi Xu, Song Chen, Bin Li, “Ant system based 3D fixed-outline floorplanning”, IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Guilin, China, Oct. 2014.

Teching

• Spring 2024: ELEC6414P - Neural Networks and Applications - USTC

• Spring 2025: ELEC6414P - Neural Networks and Applications - USTC

Project

• Thermal-Driven Placement and Routing Design for Chiplet Integration, NSFC, 2025.01-2027.12.

• Machine Learning Based Layout Generation with Multiple Constraints for Analog Integrated Circuits, NSFC, 2022.01-2023.12.

• Key Technologies for Reliability Design of Through Silicon Via in Three-Dimensional Integrated Circuits, NSFC, 2020.01-2022.12.

• Automated Optimization for Convolution Computing Circuits, Huawei, 2024.12-2025.09.

• Pin Optimization for Hierarchical Chip Design with Module Reusability, Huawei, 2025.09-2026.09.